The present invention relates generally to semiconductor devices, and more particularly, to techniques for analyzing and debugging circuitry within an integrated circuit device.
The semiconductor industry has recently experienced technological advances that have permitted dramatic increases in circuit density and complexity, and equally dramatic decreases in power consumption and package sizes. Present semiconductor technology now permits single-chip microprocessors with many millions of transistors, operating at speeds of hundreds of millions of instructions per second to be packaged in relatively small, air-cooled semiconductor device packages. A by-product of such high-density and high functionality in semiconductor devices has been the demand for increased numbers of external electrical connections to be present on the exterior of the die and on the exterior of the semiconductor packages which receive the die, for connecting the packaged device to external systems, such as a printed circuit board.
As the manufacturing processes for semiconductor devices and integrated circuits increase in difficulty, methods for testing and debugging these devices become increasingly important. Not only is it important to ensure that individual chips are functional, it is also important to ensure that batches of chips perform consistently. In addition, the ability to detect a defective manufacturing process early is helpful for reducing the number of defective devices manufactured.
Traditionally, integrated circuits have been tested using methods including directly accessing circuitry or devices within the integrated circuit. In addition, many methods require the circuit to be powered. Directly accessing the circuitry is difficult for several reasons. For instance, in flip-chip type devices, transistors and other circuitry are located in a very thin epitaxially-grown silicon layer in a circuit side of the die. The circuit side of the die is arranged face-down on a package substrate. This orientation provides many operational advantages. However, due to the face-down orientation of the circuit side of the die, the transistors and other circuitry near the circuit side are not readily accessible for testing, modification, or other purposes. Therefore, access to the transistors and circuitry near the circuit side is from the back side of the chip.
Since access to the transistors and circuitry in flip-chips is generally from the back side of the device, it is often necessary to mill through the back side and probe certain circuit elements in order to test the device. Often, the area between transistors and other circuitry in flip-chip and other integrated circuit devices is very small. Probing points between such circuitry and devices is difficult to achieve without contacting the devices between which the probes are formed and potentially causing damage. In addition, typical probes are not small enough to enable the addition of a plurality of such probes in a relatively small space. These and other difficulties inhibit the access and probing of circuit areas located between and beneath such circuitry. A related inhibition to the analysis of semiconductor devices is the lack of a readily usable manner in which to access and test the devices throughout the die. This problem continually worsens as the amount of devices within a typical semiconductor die number into the millions and are formed at distances between each other ranging in the micron or sub-micron level.
The present invention is directed to a method and system for forming a grid in a semiconductor device for improving analysis of the device involving using the grid to access and monitor various portions of the circuitry. The present invention is exemplified in a number of implementations and applications, some of which are summarized below.
According to an example embodiment of the present invention, a grid having several elongated narrow conductive via probes is formed in a semiconductor device having circuitry in a circuit side opposite a back side. The grid is created by forming a plurality of probe points extending over target circuitry in the semiconductor device. A target node in the circuitry is monitored by accessing part of the grid coupled to the target node.
According to another example embodiment of the present invention, a system is arranged for analyzing a semiconductor device having circuitry in a circuit side opposite a back side. The system includes a substrate removal device adapted to remove substrate from the semiconductor device and form an exposed region over a target node. An ion deposition device is also included and is adapted to form a grid having a plurality of probe points extending over the target node. A testing arrangement is adapted to use the grid and to monitor the device.
The above summary of the present invention is not intended to describe each illustrated embodiment or every implementation of the present invention. The figures and detailed description which follow more particularly exemplify these embodiments.